Dual-input time-delay switching circuit



United States Patent [72] Inventor Martin E. Levine Bettendorf, Iowa [21 1 Appl. No. 762,789 [22] Filed Sept. 26, 1968 [45] Patented Dec. 29, 1970 [73] Assignee Gulf & Western Industries, Inc.

New York, N.Y. a corporation of Delaware. by mesne assignments [54] DUAL-INPUT TIME-DELAY SWITCHING CIRCUIT 7 Claims, 6 Drawing Figs.

[SZI US. Cl 307/252, 307/218, 307/293, 307/305 [51] Int. Cl ..II03k 17/00 [50] Field of Search 307/252, 293, 218, 275

[56] References Cited UNITED STATES PATENTS 3,053,995 9/1962 l-lallberg 307/275 3,471,716 10/1969 Dinger 307/275 across a load after a predetermined period of time, comprising I Primary ExaminerDonald D. Forrer Assistant Examiner-David M. Caner Attorney-Meyer, Tilberry and Body ABSTRACT: There is provided a dual-input. time-delay switching circuit for switching an alternating voltage source an electronic control means, such as a triac, having a first, second, and control electrode, and exhibiting the characteristic of presenting a low impedance to current flow from the alternating voltage source to the load when a forward biasing signal is applied to the control electrode; and, circuit means for applying a forward biasing signal to the control electrode of the electronic control means. The circuit means includes a first and second actuatable switching means, for, when both are actuated, applying a forward biasing signal to the control electrode of the electronic control means; means for actuating the first actuable switching means; timing circuit means for ac- BLOCKING OSCILLATOR 42 3 TIMING CIRCUIT-TN CIRCUIT-O |o L .I u A. a l 7e '2 l 36 40 7' S 62 m l X1 58 .1 Z! 34 38 52 l6 e): w T

g .L 2 I 116 1' 9 i 84 V. E20 66? as I I08 '2 1 I06 112 92 9 f u S f} 4128 l I 'Inc i f 9s n4 LOGIC ClRCUlT L mnmnnmmm SHEET 1 [IF 2 INVENTOR. MARTIN E. LEVINE ATTORNEYS PATENTED IIEI329 I970 SHEET 2 OF 2 (PRIOR ART) ELEcTRo MECHANICAL TIII IE- DELAY I RELAY N I5 l I LL I l A c -I J MEEIE IIFC A Ti A L L TIME-DELAY OOXWO RELAY \J B D FIG. 3G (PRIOR ART) 3 soLID STATE TIME E DELAY oox T- 0 2 SWITCHING N 2 cIRcuIT T Isa FIG. 3b

A c X ELEZTRO- MECH NICAL Y TIIvIE- DELAY 00 X O RELAY N L8 2 BL T S2 FIG. 4a (PRIOR ART) SOLID T STATE A? TIME DELAY 07 SWITCHING QQXQ INVENTOR. CIRCUIT i MARTIN E. LEVINE 2 34 FIG. 4b

BY MW, M 8 86d? ATTORNEYS DUAL-INPUT TIME-DELAY SWITCHING CIRCUIT DISCLOSURE The present invention relates to the art of time-delay switching circuits, and,'more particularly, to such circuits for gating an electronic control device, 'such as a triac, into conduction at a predetermined period of time after a pair of actuating signals are applied to the circuit.

The present invention is particularly applicable as a control circuit for a triac, and will be described with particular reference thereto, although it'should be appreciated that the similar switching devices.

Solid-state switching devices, which are triggered into conduction by a gating signal, for controlling the voltage applied to a load have become an important component in a wide variety of control applications. One such device .is a siliconcontrolled rectifier. These devices are limited to use in permitting current conduction in one direction only; therefore, for alternating current applications it is necessary to employ two silicon-controlled rectifiers, poled in reverse directions with the gates of each device separately triggered. More recently, a device known as a triac, and described in Application Note 200.35, Mar.- 1966, by General Electric-Company, has been employed for controlling alternating current. The term triac is a generic term that has been given a three-electrode, alternating-current, semiconductive switch.

Dual-input, time-delay relays known heretofore for switching and alternating voltage supply source across a load, particularly when high-current capability is required, have included an electronic circuit, such as a resistor-capacitor circuit, for energizing an electromechanical load relay after a predetermined period of time to thereby couple the load across the source. As is well known, electromechanical load relays inherently have certain limitations, to wit, relatively low-speed operation, unreliable operation in adverse environments, relatively short life due to contact pitting, et cetera.

The present invention contemplates a new and improved dual-input, timedelay circuit for controlling a switching device which overcomes all of the above referred-to problems, and others, and provides a circuit which is reliable in operation. 1

In accordance with the present invention, there is provided a dual-input, time-delay switching circuit for applying a forward biasing signal to an electronic control device, such as a triac, comprising; first and second actuatable switching means, for, when both are actuated, applying a forward biasing signal to the electronic control device; means for actuating the first actuatable switching means; timing circuit means for actuating the second actuatable switching means at a predetermined time after a second level signal is applied to the timing circuit means; and, first and second input circuit means each having a first and a second condition,'for, when both are actuated to the second condition, applying a second level signal to the timingcircuit means so that at a predetermined time after the first and second circuit means areactuated to the second condition, the second actuatable switching means will beactuated. g

in accordance with the more limited aspect of the present invention, the circuit means for actuating the second'actuatable switching means includes a switch means for altering the condition that the second actuatable switching means attains at a predetermined time after the first and second input circuit means are actuated to the second condition.

The principal object of the present invention is to provide a dual-input, solid-state circuit for switching an alternating-voltage supply source across a load at a predetermined period of time after receipt of a pair of input signals.

Another object of the present invention is to provide a solidstate. dual-input, time-delay switching circuit in which the condition of the output terminals prior to timing, during timing, and upon completion of timing, may be altered by varying the position of a switch. r

A still further object of the present invention is to provide a semiconductor, dual-input, time-delay switching circuit having a relatively high current capability.

A further object of the present invention is to provide a solid-state, dual-input, time-delay relay being capable of highspeed operation, reliable operation in adverse environments, and in which the life of the relay is independent of the number of switching operations.

Another object of the present invention is to provide a semiconductor, time-delay switching circuit which is capable of operation at relatively high temperatures, i.e., in excess of A still further object of the invention is to provide a solidstate, time-delay circuit for actuating a switching device in which the gating signal takes the form of a short time-duration pulse to thereby increase the ambient temperature at which the device is capable of operation.

A further object of the present invention is to provide an improved time-delay circuit for gating atriaciinto conduction.

These and other objects and advantages of the invention will become apparentfrom the following description of the preferred embodiment of the invention as read in conjunction with the accompanying drawings in which:

FlG.-l is a schematic diagram illustrating the control circuit for gating an electronic control device, such as a triac, into conduction at a predetermined period of time in accordance with the preferred embodiment of the present invention;

FIG. 2 isa schematic circuit diagram illustrating a conventional dual-input, time-delay electromechanical relay;

FlGS. 3a, 3b, 4a, and 4b are schematic circuit diagrams illustrating various external circuitry that may be applied to the circuits illustrated in FIGS. 1 and 2. i

a Reference is now made to the drawings, wherein the showings are for the purpose of illustrating a preferred embodiment of the present invention and not for purposes of limiting same, FIG. 1 illustrates a dual'input, time-delay control circuit for gating an electronic control device, and generally comprises a timing circuit T connected through a logic circuit L and a blocking oscillator circuit 0 to thecontrol electrode of an electronic control device 10.

BLOCKING OSCILLATOR Blocking oscillator circuit 0, as I is more particularly described in U.S. Pat. application, Ser. No. 730,2 l 2, filed Apr. I6, 1968, and entitled High Temperature Semiconductor Switching Circuit, includes a resistor 14 having one terminal connected to timing circuit T and the other terminal connected through a capacitor 16 to ground. Connected to the junction between resistor 14 and capacitor 16 is one terminal of a resistor 18 having the other terminal thereof connected through a capacitor 20 to ground. Also connected to the junction between resistor 14 and capacitor 16 is one terminal of a primary winding 22 of a transformer 24. Connected to the other terminal, or the positive-polarity indicated end, of primary winding 22 is the collector of an NPN transistor 26 having its base connected through a resistor 28 to ground. Also connected to the base of transistor 26 is the cathode of a diode 30 having its anode connected to one terminal of a feedback winding 32 of transformer 24. The other terminal, or the positive-polarity indicated end, of feedbackwinding 32 is connected directly to the junction between resistor 18 and capacitor 20. The emitter of transistor 26 isconnected to one terminal of logic circuit One terminal of a secondary winding 34 of transformer 24 is connected to the control electrode 36, or gate terminal, of triac 10, and the other terminal, or positive-polarity indicated end, of secondary winding 34 is connected directly to a first terminal38 oftriac 10. A capacitor 40 is connected between the first terminal 38 and a second and 3 respectively.

TIMING CIRCUIT Timing circuit T includes an alternating-voltage supply 1 source S having one terminal connected directly to ground,

and the other terminal connected to the anode of a diode 50. The cathode of diode 50 is connected through a capacitor 52 to ground, and through a resistor 54 to one terminal of a potentiometer 56. The other terminal of potentiometer S6 is connected directly to the base of a unijunction transistor 58, and is also connected through a capacitor 60 to ground. The first base of unijunction transistor 58 is connected through a resistor 61 to ground, and the second base of this transistor is connected through a resistor 62 to the junction between resistor 54 and potentiometer 56. Also connected to the first base of unijunction transistor 58 is a control electrode 64 of a silicon-controlled rectifier 66. The cathode of silicon-controlled rectifier 66 is connected directly to ground, and the anode of this device is connected through a pair of series-connected resistors 68 and 70 to the junction between resistor 54 and potentiometer 56.

Connected to the base of unijunction transistor 58 is the anode of a diode 72 having its cathode connected to the anodes of a pair of diodes 74 and 76. The anodes of diodes 74 and 76 are also connected to the junction between resistors 68 and 70.

LOGIC CIRCUIT Logic circuit L includes a first input terminal 1 connected to the anode of a diode 80 having the cathode thereof connected through a resistor 82 to the base of an NPN transistor 84. Connected to the junction between diode 80 and resistor 82 is one terminal of a capacitor 86 having the other terminal thereof connected to ground. Also, the base of transistor 84 is connected through a resistor 88 to ground. I

The emitter of transistor 84 is connected directly to the collector of an NPN transistor 90 having its emitter connected to ground. The base of transistor 90 is connected through a resistor 92 to the cathode of a diode 94. The anode of diode 94 provides a second input terminal 2. The base of transistor 90 is also connected through a resistor 96 to ground, and the junction between resistor 92 and diode 94 is connected through a capacitor 98 to ground.

The collector of transistor 84 is connected through a resistor 100 to the base of an NPN transistor 102 having the emitter thereof connected directly to ground. The collector of transistor 102 is connected to the cathode of diode 72. Also,

connected to the collector of transistor 84 is one terminal ofa resistor 104 having the other terminal thereof connected to the junction between diode 50 and resistor 54.

The junction between diode 80 and capacitor 86 is connected through a resistor 106 to the base of an NPN transistor 108 having the emitter thereof connected directly to the collector of an NPN transistor 110. The base terminals of transistors 108 and 110 are connected through a pair of resistors 112 and 114, respectively, to ground. The emitter of thereof connected to the junction between diode 50 and resistor 54. The junction between diode 116 and resistor 118 is connected directly to the cathode of diode 74 and provides a terminal 7 of a rotary-type switch 130. Also, the collector of transistor 120 is connected through a diode 126, poled as shown in'FIG. 1, to a terminal 6 of switch 130. The collector of transistor 120 is also connected through a resistor 128 to the base of transistor 110. The cathode of diode 76 provides a terminal 8 of switch 130.

Rotary-type switch 130 also includes a movable arm 9 connected through a resistor 132 to the base of an NPN transistor 134. The base of transistor 134 is connected through a resistor 136 to ground, the emitter is connected directly to ground, and the collector of this transistor is connected to the emitter of transistor 26 in blocking oscillatoncircuit O.

OPERATION OF BLOCKING osctt'tAToR ClRCUlT The signal supplied by alternating-voltagesupply source S is rectified through the network comprisediof diode 50, capacitor '52,'resistoi's 54 and 14, and capacitor 16, to thereby provide a direct current signal which will charge capacitor 20 through resistor 18, and will also cause transformer 24 to begin to store energy in primary winding 22. As energy is gradually stored-in primary winding'22, a positive voltage of increasing amplitude is induced in feedback winding 32 of the polarity indicated-with reference to the polarity dot. The voltage induced in feedback winding 32 is applied through diode 30 to gradually forward bias transistor 26 into conduction. Once transistor 26 commences to conduct, capacitor 20 rapidly discharges through primary winding 22 and transistors 26 and 134 to ground, assuming transistor 134 is forward biased into conduction. 1

When capacitor 20 discharges through primary winding 22, a voltage impulse of short duration is developed across primary winding 22 which in turn induces a similar pulse in secondary winding 34, to thereby apply a short duration gating signal to control electrode 36 of triac 10. This gating signal causes triac 10 to switch from an off to an *on" condition. l'n-the on" condition, a closed path is completed between terminals 3 and 4, which path will be maintained until an alternatingvoltage signal supplying a load passes through approximately a zero-voltage level. Because the gating pulse is of a very short duration, excessive current is not applied to the control electrode 36 of triac 10, and operation at high temperature is made possible.

Also, upon saturation of the core of transformer 24, the induced current through feedback winding 32 terminates, and the forward biasing signal applied to transistor 26 terminates, to thereby cause this transistor to again become reverse biased. Once transistor 26 becomes reverse biased, capacitor 20 will again begin to charge to thereby commence another cycle of operation.

When transistor 134 is reverse biased, the oscillator circuit including transistor 26 will cease to oscillate since there will be no path for the discharge of capacitor 20. Transistor 134 is actuated by the signal supplied from timing circuit T and logic circuit L.

OPERATION OF TlMlNG Awb'to'crc CIRCUITS Prior to the time an alternating-current signal is applied to:- input terminals 1 and 2, transistors 84 and are reverse biased thereby causing a binary l signal to be applied to the base of transistor 102. By a binary l signal is-meant a signal of some positive potential, and by a binary 0" signal is meant a signal equal to approximately ground potential. When a binary 1 signal. is applied to the base of transistor 102, this transistor becomes forward biased to thereby cause capacitor 60 to discharge and remain discharged through diode 72 and transistor 102. Transistors 108 and are also reverse; biased, thereby tending to cause transistor 102 to remain in a, forward biased condition. During this condition, a binary l "r; signal will be applied through resistor 104, diode 116, and re sistor 118 to the base of transistor 120, thereby forward biasing this transistor into conduction. With transistor in a, conductive state, a binary 0 signal will be applied to ter-l minal 6 of switch 130. The binary. f 1 signal applied to the base of transistor 120 will be applied to terminal 7 of switch. 130, and the binary 0 signal applied to the anode of diode. 76 will be applied to terminal8 of switch 130. l,

Upon application of an altemating-current signal to input terminal 1, in the absence of a signal being applied to terminal 2. transistor 84 will become forward biased; however, since transistor 90 remains reverse biased, transistor 102 will remain in a forward biased condition. With transistor 102 forward biased the signals applied to the remainder of the circuit will remain unchanged. Similarly. if an altemating-current signal is applied to terminal 2. in the absence of a signal being applied to terminal I, transistor 90 will become forward biased; however, since transistor 84 will remain reverse biased, transistor 102 will remain forward biased and the signals applied to the remainder of the circuit will remain unchanged.

When an alternating-current signal is applied simultaneously to terminals 1 and 2, a timing cycle commences and transistors 84 and 90 will become forward biased, thereby causing a binary 0" signal to be applied to the base of transistor 102. When a binary 0" signal is applied to the base of transistor 102, this transistor will become reverse biased, thereby allowing capacitor 60 to commence charging through potentiometer 56. As is readily apparent, the impedance of potentiometer 56 may be varied to alter the charging time of capacitor 60. When a signal is applied to terminals 1 and 2, a binary 1" signal will be applied to the anodes of diodes 74 and 76, thereby causing binary l signals to be applied to terminals 7 and 8 of switch 130. The binary l signal applied to the base of transistor 120 will remain during the timing cycle; therefore, the signal appearing terminal 6 of switch 130 will remain at a binary 0" level.

The timing cycle will terminate when the voltage developed across capacitor 60 attains a level sufficient to cause unijunction transistor 58 to fire or avalanche," and this will cause a voltage to be developed across resistor 61 to thereby gate silicon control rectifier 66 into conduction. When silicon-controlled rectifier becomes conductive, binary 0 signals will be applied to the anodes of diodes 74 and 76. With binary 0" signals will be applied to terminals 7 and 8 of switch 130. Also, with a binary 0" signal developed at the anode of diode 74, a binary "0" signal will be applied to the base of transistor 120 causing this transistor to become reverse biased, thereby causing a binary l signal to appear at terminal 6 of switch 130.

Once silicon-controlled rectifier 66 becomes conductive, this device will remain conductive until the slightly positive signal applied to the anode with respect to the cathode is removed. As may be apparent, controlled rectifier 66 will remain conductive. and the signals applied to terminals 6, 7 and 8 of switch 130 will remain in at timed-out condition until transistor 102 is again forward biased. Thus, after time-out, a binary l signal will be applied to the base of transistor into conduction. and if a signal is applied to transistor 108 to cause this transistor to remain conductive, transistor 102 will remain reverse biased. Therefore, if after time-out, the alternatingcurrent signal applied to terminal 1 remains, the signal applied to terminals 6, 7 and 8 of switch 130 will remain in the timedout condition until the alternating-voltage signal applied to terminal 1 is removed. If however, the signal applied to terminal 1 is removed immediately after time-out, the circuit will be automatically reset to a condition similar to that prior to the time the timing cycle commenced.

When a binary 0 signal appears at terminal 6 of switch 130, assuming movable arm 9 is in the position illustrated in FIG. 1, a binary 0" signal will be applied to the base of transistor 134, thereby reverse biasing this transistor. If a binary l signal appears at terminal 6 of switch 130, transistor 134 will be forward biased into conduction, thereby commencing operation of blocking oscillator circuit 0.

In accordance with the preferred embodiment of the invention, the binary signals appearing at input terminals 1 and 2 and the conditions of output terminals 3 and 4 during each of the timing phases are illustrated in table l.

IABLE I Signal al terminals Timing Cycle l 3 Reference is now made to FIGS, 2, 3, and 4 which illustrate an analogy between the dual-input, time-delay switching circuit of the present invention and electromechanical timedelay relay. FIG. 2 shows an electromechanical time-delay relay such as the Cycle-flex Reset Timer, I-IP-S Series, illustrated in Bulletin of The Eagle Signal Industrial Customer Catalog. This relay includes a clutch solenoid connected between one input terminal A and one terminal of a timing motor 152. The other terminal of motor 152 is connected through a set of normally-closed delay contacts 154 to the other input terminal B. A pair of output terminals C and D are connected through a set of normally-open delay contacts 156. FIGS. 3a and 3b illustrate similar external circuitry applied to an electromechanical time-delay relay such as that illustrated FIG. 2, and a solid-state time-delay switching circuit similar to that illustrated in FIG. 1. It should be noted that the external circuitry is identical with both circuits and the output signals takes the same form. With this circuit arrangement, the circuit between output terminals C-D and 34 takes the form of an open circuit prior to time-out, a closed circuit at timeout, and remain a closed" circuit until switches LS-l and LS- 3, respectively, are opened.

FIGS. 4a and 4b illustrate an external connection in which the output terminals C-D and 3-4 of the time-delay relay and switching circuit, respectively, return automatically from the timed-out condition to the condition prior to timing. For example, timing commences when limit switches LS-2 and L5- 4 close, and at the end of a timing cycle the circuits between terminals CD and 3-4 take the form of a closed circuit. After time-out, even though the limit switches LS-2 and LS-4 remain closed, the circuits between the output terminals return to the reset" condition automatically.

Although the invention has been shown in connection with a preferred embodiment, it will be readily apparent to those skilled in the art that various changes in form may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Iclaim:

1. A dual-input time-delay switching circuit for switching an alternating voltage source across a load after a predetermined period of time comprising:

static switch means having a first, a second, and control electrode, said switch means exhibiting the characteristic of presenting a low impedance to current flow from a said alternating voltage source to a said load when a forward biasing signal is applied to said control electrode; and

circuit means for applying a said forward biasing signal to said control electrode of said static switch means including:

generating means and actuatable switching means, for, when both are actuated, applying a said forward biasing signal to said control electrode of said static switch means;

means for actuating said generating means;

timing circuit means for actuating said actuatable switching means at a predetermined time after receipt of a control signal; and,

first and second input circuit means, each having a first and second condition, for, when both are actuated to said second condition, applying a said control signal to said timing circuit means so that said actuatable switching means is actuated at a predetermined time after said first and said second input circuit means are are actuated to said second condition.

2. A time-delay switching circuit as defined in claim 1 wherein said timing circuit means includes a timing capacitor for storing a voltage, and an electronic control means having a first, second, and control electrode, said first electrode of said electronic control means being adapted to be coupled to a source supply, said second electrode being coupled to said actuatable switching means, and said control electrode being coupled to said capacitor so that when the value of said stored voltage attains a value equal to a characteristic value, an output signal will be applied to said second actuatable switching means to thereby actuate said switching means.

3. A time-delay switching circuit as defined in claim 2 wherein said static switch means is a triac;

said generating means and actuatable switching means includes second and third electronic control means, respectively, each control means having first, second, and control electrodes; and,

said biasing circuit means includes a circuit means for coupling said control electrode of said third electronic control means to said second electrode of said first electronic control means.

4. A time-delay switching circuit as defined in claim 3 wherein said second and third electronic control means have a first and a second condition, said second and third electronic control means being coupled to said control electrode of said static .switch means so that when said second and third control means are actuated to said second condition a forward biasing signal is applied to said control electrode of said static switch means; and, said coupling circuit means includes a switch means for altering the condition that said third electronic control means takes at a predetermined time after said first and second input circuit means are actuated to said second condition.

5. [n a triac switching circuit for switching an alternating voltage source across a load after a predetermined period of time comprising:

circuit means for applying a forward biasing signal to a said triac including;

generating and actuatable switching means, for, when both are actuated. applying a said forward biasing signal to a said triac;

means for actuating said generating means;

timing circuit means for actuating said actuatable switching means at a predetermined time after a control signal is applied to said timing circuit means; and,

first and second input circuit means each having a first and a second condition, for, when both are actuated to said second condition, applying a said control signal to said timing circuit means so that at a predetermined time after said first and second circuit means are actuated to said second condition said actuatable switching means will be actuated.

6. In a triac switching circuit as defined in claim 5 wherein said means for actuating said generating means is a means for periodically, and at a given frequency, actuating said generating means; said generating means and actuatable switching means have a first and second condition and are adapted to be coupled to a said triac so that when said generating means and actuatable switching means are actuated to said second condition a said forward biasing signal is applied to a said triac; and, said circuit means includes a switch means for altering the condition that said actuatable switching means takes at a predetermined time after said first and second input circuit means are actuated to said second condition.

7. In a triac switching circuit as defined in claim 5 wherein said means for actuating said generating means includes a transformer having a primary and a secondary winding, said primary winding being coupled across a source supply when said generating means and actuatable switching means are actuated, said secondary winding adapted to be coupled to a said triac; and, said first and second input circuit means each include first and second electronic control means each having a first, second, and control electrode, said first and second electrodes of said electronic control means being coupled to said timing circuit, for, when both are actuated to said second condition, a said control signal is applied to said timing circuit means, and said control electrode of said first and second electronic control means provide a first and second input terminal respectively for said biasing circuit means. 

